This invention relates to digital differential analyzers (DDA) and particularly to a DDA which is connected through a direct memory access bus to a host processor to receive a parameter defining an arithmetic operation and data from the host processor and to process a differential analysis as a digital operation.
The DDA is supplied with input variables of a digitized form to which voltages and currents used in analog computers are converted, and produces at its output a quantized digital signal of finite increments which occur with the change of the input variables, on the basis of sectional quadrature.
In general, the calculation of the following expression, ##EQU1## is approximately determined as ##EQU2## by applying the sectional quadrature to its geometrical contents. Thus, the equivalent operation of Eq. (2) can be performed for the above-mentioned digital signal by the digital formation of all the arrangements.
For simple and economical arrangement, a set of fundamental arithmetic circuits are provided, and the results of the operation are obtained as a constant increment from the set of the circuits and written into an operation result memory called the .DELTA.Z memory. The set of arithmetic circuits is formed for various operation elements and operated by an operation-mode command. To the inputs of the operation elements are applied the contents of the .DELTA.Z memory, and the results of operation therein are again stored in the .DELTA.Z memory. Thus, it is suitable to perform data access operation between the operation elements through the .DELTA.Z memory. Therefore, the DDA employs a set of arithmetic circuits the function of which is specified when a necessary operation function is requested at each stage of a sequence of operations. The results of operation at the preceding stage is used as an operation input, and thus the set of arithmetic circuits are used in time sharing, or in a serial manner.
For operation of the DDA, it is necessary to specify predetermined operation elements, or integrators, multipliers, adders and so on and determine how the inputs and outputs of the operation elements are interconnected. The key board provided in the DDA is operated, or the host processor connected through the direct memory access bus (DMA) is used, thereby to specify the functions of the operation elements at each stage of operation. Information for interconnecting the operation elements is applied to the DDA and stored in the memory within the DDA. This stored information is used for sequential performance of the arithmetic operation.
In the system in which the DDA is controlled by the host processor, the host processor and the DDA are interconnected through the DMA bus, and the DDA includes a hardware only for arithmetic operation, or a DDA processor. The host processor first transfers a parameter for defining the arithmetic operation to the DDA processor to start operation.
The DDA processor, when having finished the arithmetic operation of DDA, interrupts the host processor, and transmits its solution by the input-output control through the DMA bus.
In the conventional system, the host processor is needed to transfer an operation parameter and solution data at each operation and control the start of the DDA processor. Since the software program for the host processor is frequently executed, the load rate of the processor and DMA bus is increased, and response speed is decreased.
Particularly in the application where a plurality of DDA operations are needed to be processed at a time and at a high speed, it is necessary to provide a plurality of DDAs, which is uneconomical. Besides, a complex subroutine including a plurality of DDA operation processes, or the like remarkably reduces the response time.